1. Technical Field
The invention relates generally to ratio-logic systems, and more specifically, to input sensing circuits for low power ratio-logic systems.
2. Background Art
Ratio-logic circuits, such as Programmable Logic Arrays (PLA) or custom control paths, are used in microprocessor design for several reasons. Two reasons include: ratio-logic circuits perform logic functions at a high speed; and ratio-logic circuits provide circuitry that may be used in a compact layout. One disadvantage, though, of using ratio-logic circuits in any device is the large amount of power consumed, which is caused by the DC current paths that exist in the circuit.
As described in U.S. Pat. No. 4,233,667, "Demand Powered Programmable Logic Array", issued to Devine et al. on Nov. 11, 1980, static PLA power is reduced by synchronously decoding the logical inputs to determine if the PLA is required to perform a computation. If certain sections of the PLA do not need to perform any computations, those sections are powered down. Although PLA power is reduced in the above-mentioned patent, the PLA cannot be completely powered down, because only certain sections of the PLA are disabled. Furthermore, the delay that occurs by first clocking and then decoding the logical inputs could impede the performance of the circuit. In addition, the power-reducing elements of the aforementioned circuit are not self-contained and therefore are not conducive to other PLA or ratio-logic designs.
Other examples of ratio-logic systems with power reducing circuits include: U.S. Pat. No. 5,033,017, "Programmable Logic Array with Reduced Power Consumption", issued to Taniai et al. in July 1991; and U.S. Pat. No. 5,311,079, "Low Power, High Performance PLA", issued to Ditlow et al. in May 1994. Although different techniques are discussed for reducing power in PLAs, the aforementioned patents either use power reduction devices that clock their inputs, and/or do not allow for a complete evaluation of all inputs by the ratio-logic circuit.
Accordingly, a need has developed in the art for a low power ratio-logic system that provides asynchronous input sensing circuitry for reducing power in a variety of ratio-logic circuits and provides complete evaluation of all the inputs by the ratio-logic circuit.